Light-emitting semiconductor chips are known whose electrical connections are all arranged on a main surface by which the semiconductor chips are in each case mounted on carriers. Such semiconductor chips, which have the advantage that, for example, additional electrical contacts, for instance in the form of bonding wires, are no longer necessary for the electrical connection, are also designated as so-called “flip-chips”.
Since a flip-chip is typically mounted on a carrier only by way of its electrical connections, the problem arises of effectively dissipating heat from the semiconductor chip during operation.
It is known to mount a flip-chip onto a ceramic substrate, for example, wherein the electrical connections are placed onto corresponding conductor tracks of the ceramic substrate and connected to them. The advantage of a ceramic substrate is that it is electrically insulating and highly thermally conductive, and that the coefficient of thermal expansion can be chosen such that it is similar to the semiconductor chip. For connecting the semiconductor chip to the conductor tracks of the ceramic substrate, various possibilities are appropriate, for example, soldering, gold-on-gold ultrasonic bonding, adhesive bonding or sintering at a low temperature (LTS: “low temperature sintering”). However, contrasting drawbacks include increased costs, in particular in the case of large-area ceramic substrates, and a problematic adaptation of the coefficient of thermal expansion to a further heat sink, a so-called second-level heat sink, for example, a metal-core circuit board, onto which the mounted semiconductor chip with the ceramic substrate is mounted.
Furthermore, housings of the so-called QFN design (QFN: “quad flat no leads”) are known, which have leadframe parts in a plastic housing on which, for example, a flip-chip can be mounted. In this case, connecting possibilities such as those described for the ceramic substrate can be used, but a QFN housing has a better thermal conduction than a ceramic substrate and is also more cost-effective than the latter. Furthermore, the adaptation of the coefficient of thermal expansion to a second-level heat sink is better than in the case of a ceramic substrate. What is disadvantageous about a QFN housing, however, is that the coefficient of thermal expansion of the housing deviates significantly from that of the semiconductor chip, which can lead to reliability problems. Moreover, the achievable minimum feature sizes in the case of QFN housings are limited by the minimum etching width of a leadframe and are more than 100 μm, for example, in the case of a 200 μm thick leadframe.
In order to attain an electrically insulating mounting side for a QFN housing, a dielectric layer, for example, composed of diamond-like carbon (DLC) or polyimide, additionally has to be applied, which has to be covered with an additional metal layer, for example, in order to be able to mount the QFN housing, for example, by soldering. As a result, although an electrical insulation of the underside of the QFN housing can be achieved, materials suitable for the insulation are associated with higher costs and often also with a poorer thermal conductivity.
With an increased effort in terms of process engineering, it is also possible to implement a QFN housing with a suitable electrical insulation on a side facing the semiconductor chip.